Position: Ph.D. Candidate
Current Institution: Princeton University
Highly Configurable Architecture for the Cloud
Businesses and Academics are increasingly turning to Infrastructure as a Service (IaaS) Clouds to fulfill their computing needs. Unfortunately, current IaaS systems provide a severely restricted pallet of rentable computing options which do not optimally fit the workloads that they are executing. We address this challenge by proposing a highly configurable architecture that encompasses various aspects (the Sharing Architecture, MITTS, CASH) of computer architecture. We design and evaluate a manycore architecture, called the Sharing Architecture [ASPLOS 2014], specifically optimized for IaaS systems by being reconfigurable on a sub-core basis. The Sharing Architecture enables better matching of workload to micro-architecture resources by replacing static cores with Virtual Cores which can be dynamically reconfigured to have different numbers of ALUs and amount of Cache. While memory bandwidth has become a critical resource in multicore and manycore processors, current IaaS Clouds lack the ability to provision memory bandwidth on a per-customer basis according to customers’ need and payment. MITTS (Memory Inter-arrival Time Traffic Shaping) [ISCA 2016] is a distributed hardware mechanism which limits memory traffic at the source (Core or LLC). MITTS shapes memory traffic based on memory request inter-arrival time using novel hardware, enabling fine-grain bandwidth allocation. In an IaaS system, MITTS enables Cloud customers to express their memory distribution needs and pay commensurately. In a general purpose multicore program, MITTS can be used to optimize for memory system throughput and fairness. MITTS has been implemented in the 32nm 25-core Princeton Piton Processor [HotChip 2016], as well as the open source OpenPiton [ASPLOS 2016] processor framework. The Sharing Architecture and MITTS provide fine-grain hardware configurability, which improves economic efficiency in IaaS Clouds. However, cloud customers must determine how to use such fine-grain configurable resources to meet quality-of-service (QoS) requirements while minimizing cost. This is especially challenging for non-savvy customers. We propose CASH [ISCA 2016], a runtime system that uses a combination of control theory and machine learning to configure the architecture such that QoS requirements are met and the cost is minimized. The presentation will be about these three major elements (The Sharing Architecture, MITTS, and CASH) along with my thesis project “COMPAC: Composable Hardware Accelerators”, which addresses using composable hardware accelerators in the IaaS Cloud. I will present how to co-design the hardware and software in a highly configurable manner to improve IaaS Cloud economic efficiency.
I am the first graduate student of Prof. David Wentzlaff. My research area is computer architecture, operating system, and parallel computing. I got my Bachelor’s degrees in Electrical Engineering, Computer Engineering, and Mathematics from University of Michigan and Shanghai Jiao Tong. I worked at Microsoft Research as a research intern for two summers. Apart from research, I like playing tennis, basketball, swimming, yoga, to name a few . And I love both classical music and pop music. I have been playing the violin for over ten years.