Position: Analog Engineer

Current Institution: Intel

Ultra-Low Power Multi-Channel Data Conversion with a Single SAR ADC for Mobile SensingApplications

Traditional data compression for sparse signals like bio-signals and image signals is subsequent to front-end Nyquist-rate data sampling. Recently emerging compressive sensing (CS) theory suggests that the signal sparsity can be exploited to enable sub-Nyquist rate sampling and thus save commensurate power and hardware-complexity of the front-end sensor. Although in recent years CS has been actively exploited to reconstruct a single-channel signal at sub-Nyquist rate in the applications of cognitive radios and bio-sensors, very few previous works cover its feasibility on multi-channel ADCs. Besides, most previous single-channel works use active components like integrators and op-amps to perform the weighted summation operation required by the CS process, which is area and power-consuming and severely limits the linearity. An area and power-efficient, high linearity architecture for multi-channel CS-based ADC is potential. Our work proposes a CS-based SAR ADC which is capable of simultaneously converting 4-channel sparse signals at the Nyquist rate of one channel. The chip is fabricated in a 0.13μm CMOS
process. Operating at 1MS/s, the SAR ADC itself achieves a 66dB SNDR and a 25fJ/step FoM at 0.8V. Using convex optimization methods, 4- channel 500kHz-bandwidth signals can be reconstructed with a 66dB peak SNDR and a 41% max occupancy, leading to an effective FoM per channel of 6.25 fJ/step.

Wenjuan Guo received the B.S. degree from Tsinghua University, Beijing, China, in 2011 and the Ph.D. degree from The University of Texas at Austin, TX, USA, in 2016. Her Ph.D. dissertation is focused on ultra-low-power high performance SAR ADC design. During her Ph.D., she taped out three chips. After Ph.D. graduation, she continued to work with her supervisor, Dr. Nan Sun, as a Post-Doctoral Fellow and extended her research to high-resolution time-to-digital converter (TDC) design. Within 3 months, she taped out another two chips. From June 2013 to May 2014, she was a Design Intern in the DAC team of Texas Instruments, Dallas, TX. She worked on a 16-bit R-2R DAC design. She received Texas Instrument Fellowship in 2014 and 2015. Currently she is an analog design engineer in the analog-and-mixed-signal team of Intel, Austin, TX, USA.